VSC6134
Datasheet
3.8
Digital Wrapper Overhead Processor and FEC Performance
Monitor Registers
3.8.1
Drop Decoder Bit Error Interrupt Mask Register
Address:
0x700
Register Reset Value:
0xFC00
Table 202. Drop Decoder Bit Error Interrupt Mask Register
Reset
Value
Bit
Name
Access
Description
15
StFEC_ERRM
R/W
1: Interrupt for StFEC_ERR is masked.
0: Interrupt for StFEC_ERR is not masked.
1
1
1
1
1
1
0
14
13
12
11
10
9:0
EFEC_ERRM
EFEC4_ERRM
EFEC3_ERRM
EFEC2_ERRM
EFEC1_ERRM
Reserved
R/W
R/W
R/W
R/W
R/W
RO
1: Interrupt for EFEC_ERR is masked.
0: Interrupt for EFEC_ERR is not masked.
1: Interrupt for EFEC4_ERR is masked.
0: Interrupt for EFEC4_ERR is not masked.
1: Interrupt for EFEC3_ERR is masked.
0: Interrupt for EFEC3_ERR is not masked.
1: Interrupt for EFEC2_ERR is masked.
0: Interrupt for EFEC2_ERR is not masked.
1: Interrupt for EFEC1_ERR is masked.
0: Interrupt for EFEC1_ERR is not masked.
3.8.2
Drop Decoder Bit Error Status Register
Address:
0x701
Register Reset Value:
0x0000
Table 203. Drop Decoder Bit Error Status Register
Reset
Value
Bit
Name
Access
Description
15
StFEC_ERRS
R/W
Reed Solomon decoder bit error status.
An error from the Reed Solomon Decoder sets this bit and
produces a maskable interrupt.
0
0
0
14
13
EFEC_ERRS
EFEC4_ERRS
R/W
R/W
Enhanced FEC decoder bit error status.
An error from any of the four EFEC Decoders sets this bit
and produces a maskable interrupt.
Enhanced FEC Decoder 4 bit error status.
An error from Enhanced FEC Decoder 1 sets this bit and
produces a maskable interrupt.
280 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
