VSC6134
Datasheet
3.7.2
Drop Decoder Interrupt Mask Bit Register
Address:
0x220
Register Reset Value:
0x8000
Table 192. Drop Decoder Interrupt Mask Bit Register
Reset
Value
Bit
Name
Access
Description
15
DROP_FIFO_SPILLM
R/W
1: Interrupt for DROP_FIFO_SPILL is masked.
0: Interrupt for DROP_FIFO_SPILL is not masked.
1
14:0
Reserved
RO
0x0000
3.7.3
Drop Decoder Alarm Bit Register
Address:
Register Reset Value:
0x221:
0x0000
Table 193. Drop Decoder Alarm Bit Register
Reset
Value
Bit
15
Name
Access
R/W
Description
DROP_FIFO_SPILL
Reserved
1: A FIFO overflow or underflow has occurred
0
14:0
RO
0x0000
3.7.4
Add/Drop Framing Byte (A1) Capture Register
Address:
0x8B0: Add Path
0x230: Drop Path
0x0000
Register Reset Value:
Table 194. Add/Drop Framing Byte (A1) Capture Register
Reset
Value
Bit
Name
Access
Description
15:8
[ADD/DROP]_A1_2
RO
The second A1 byte of the OTU framing pattern
A1A1A1A2A2A2 where A1 = 0xF6 and A2 = 0x28. This
byte is captured from the data stream leaving RS
Decoder 2 on every multi-frame start.
0x00
7:0
[ADD/DROP]_A1_3
RO
The third A1 byte of the OTU framing pattern
A1A1A1A2A2A2 where A1=0xF6 and A2=0x28. This byte
is captured from the data stream leaving RS Decoder 2 on
every multi-frame start.
0x00
276 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
