VSC6134
Datasheet
3.7
FEC Decoder Registers
The following sections describe the FEC decoder registers. In a few instances, the references are also
made to the add path registers. In such cases, two addresses are shown in the register address field. Drop
path decoder addresses are in the 0x200+ range and add path decoder addresses are in the 0x8B0+
range.
3.7.1
Drop Decoder General Configuration Register
Address:
0x200
Register Reset Value:
0x3800
Table 191. Drop Decoder General Configuration Register
Reset
Value
Bit
Name
Access
Description
15
AUTO_DATA0_LOS
R/W
1: Zeros are inserted into decoder when LOS is detected.
0: No action taken on data into decoder when LOS is
detected.
0
0
1
14
13
AUTO_DATA0_LOF
R/W
R/W
1: Zeros are inserted into decoder when LOF is detected.
0: No action taken on data into decoder when LOF is
detected.
AUTO_NFA_FIFOSPILL
1: The drop FEC frame aligner is forced to reframe and
assert a new NFA (or a FIFO pointer reset is asserted; see
bit 11) whenever a FIFO overflow/underflow is detected.
0: FIFO overflow or underflow is still detected and its alarm
asserted, but no action is taken.
12
11
FIFOSPILL_NFAONLOCK
R/W
R/W
1: If the AUTO_NFA_FIFOSPILL bit is high, a FIFO Spill
detection forces a new NFA or a FIFO pointer reset (see
bit 11) only if PLL/RLL is in lock.
0: If the AUTO_NFA_FIFOSPILL bit is high, a FIFO Spill
detection forces a new NFA or a FIFO pointer reset (see
bit 11) independent of PLL/RLL lock status.
1
1
NFA_FPRN
1: If the AUTO_NFA_FIFOSPILL bit is high, a new frame
alignment (NFA) is forced on a FIFO over/underflow.
0: IF the AUTO_NFA_FIFOSPILL bit is high, a
FIFO_POINTER_RESET is forced on a FIFO overflow or
underflow. The FIFO_POINTER_RESET mode of this bit
should only be used when the drop decoder is in
FEC_BYPASS mode (as declared by FECDEC_MODE in
reg 0x006).
10:0
Reserved
RO
0x0000
275 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
