VSC6134
Datasheet
3.7.5
Add/Drop Framing Byte (A2) Capture Register
Address:
0x8B1: Add Path
0x231: Drop Path
0x0000
Register Reset Value:
Table 195. Add/Drop Framing Byte (A2) Capture Register
Reset
Value
Bit
Name
Access
Description
15:8
[ADD/DROP]_A2_1
RO
The first A2 byte of the OTU framing pattern
A1A1A1A2A2A2 where A1 = 0xF6 and A2 = 0x28. This
byte is captured from the data stream leaving RS
Decoder 2 on every multi-frame start.
0x00
7:0
[ADD/DROP]_A2_2
RO
The second A2 byte of the OTU framing pattern
A1A1A1A2A2A2 where A1=0xF6 and A2=0x28. This byte
is captured from the data stream leaving RS Decoder 2 on
every multi-frame start.
0x00
3.7.6
RLL Control Register
Address:
0x32F
Register Reset Value:
0x8000
Table 196. RLL Control Register
Reset
Value
Bit
Name
Access
R/W
Description
15:13
CLK_DIV[15:13]
Controls pulse size (155 MHz pulse divided by CLK_DIV).
The setting of this register depends on the gain bandwidth
product of the OpAmp used in the loop filter.
000: Reserved
100
001: Pulses at 155.52 MHz (do not use)
010: Pulses at 77.76 MHz
011: Pulses at 38.88 MHz
100: Pulses at 19.44 MHz
101: Pulses at 9.72 MHz
110: Pulses at 4.86 MHz
111: Pulses at 2.43 MHz
12
ACT_START
R/W
On the rising edge initial charge interval is asserted. This
bit should not be asserted until proper FEC frame
alignment to the incoming Drop path data stream is
achieved. When this bit is low, the RLL controller state
machine for asynchronous demapping is held in a reset
state.
0
11
Reserved
Reserved
0
10:0
0x000
277 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
