VSC6134
Datasheet
Table 203. Drop Decoder Bit Error Status Register (continued)
Reset
Value
Bit
Name
Access
Description
12
EFEC3_ERRS
R/W
Enhanced FEC Decoder 3 bit error status.
An error from Enhanced FEC Decoder 1 sets this bit and
produces a maskable interrupt.
0
0
0
0
11
10
EFEC2_ERRS
EFEC1_ERRS
Reserved
R/W
R/W
RO
Enhanced FEC Decoder 2 bit error status.
An error from Enhanced FEC Decoder 1 sets this bit and
produces a maskable interrupt.
Enhanced FEC Decoder 1 bit error status.
An error from Enhanced FEC Decoder 1 sets this bit and
produces a maskable interrupt.
9:0
3.8.3
Add Decoder Bit Error Interrupt Mask Register
Address:
0xF00
Register Reset Value:
0x8000
Table 204. Add Decoder Bit Error Interrupt Mask Register
Reset
Value
Bit
Name
Access
Description
15
StFEC_ERRM
R/W
1: Interrupt for StFEC_ERR is masked.
0: Interrupt for StFEC_ERR is not masked.
1
14:0
Reserved
RO
0x0000
3.8.4
Add Decoder Bit Error Status Register
Address:
0xF01
Register Reset Value:
0x0000
Table 205. Add Decoder Bit Error Status Register
Reset
Value
Bit
Name
Access
Description
15
StFEC_ERRS
R/W
Reed Solomon decoder bit error status.
An error from the Reed Solomon decoder sets this bit and
produces a maskable interrupt.
0
14:0
Reserved
RO
0x0000
281 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
