VSC6134
Datasheet
2.5.8
Scrambler
This block scrambles the 64-bit wide data word using a frame synchronous scrambler with a length of
6
7
127 bits and a generating polynomial 1 + x + x . The entire frame, except for the first row of the
section overhead, is scrambled. The scrambler is reset to 111111 on the most significant bit (MSB) of
the byte following the last byte of the first row of the section overhead. The scrambler is disabled (data
is passed through the block transparently) when the configuration control bit TX_SCRENA is set to 0.
The scrambler block I/O is shown in the following table.
Table 13. SDH/SONET Scrambler I/O Description
Name
Direction
Function
RESETN
CLK
IN
IN
IN
Active low reset.
155 MHz system clock.
DATAI[63:0]
155 Mbps input data bus. DATAI is clocked in on the rising edge of CLK.
Bit 63 is the MSB.
DATAO[63:0]
TX_SCRENA
OUT
IN
155 Mbps output data bus. DATAO is clocked out on the rising edge of
CLK. Bit 63 is the MSB.
When set to 1, scrambling is performed on the data. When set to 0,
scrambling is by-passed.
ROWCNT[3:0]
COLCNT[6:0]
SETCNT[4:0]
IN
IN
IN
Tx STS-192/STM-64 frame row counter (rows 0 to 8).
Tx STS-192/STM-64 frame column counter (columns 0 to 89).
Tx STS-192/STM-64 frame set counter (sets 0 to 23).
2.5.9
Section Overhead Generator Registers
For information about the registers for the section overhead generator, see “Section Overhead Generator
Registers,” page 251.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
