VSC6134
Datasheet
A diagram of the receive overhead extraction block is shown in the following figure.
Figure 13. Rx Serial Overhead Interface Diagram
AD/DRRXSDHOHD
AD/DRRXSDHOHFS
Clock-Crossing Logic
CLK155
8
8
DI1
DO
Output
DI2
Logic
and
8
SEF
WE
Register
Stages
WA1
WA2
Fail
8
Input
Logic
Reg File
DataIn
Setcnt
RA
(Input Bus
Decoding,
Register
Stages,
and Write
Counter)
5
cnt_rst
Colcnt
3
DI1
DI2
WE
DO
Rowcnt
5
5
Read
Address
Counter
5
5
WA1
WA2
Reset_n
(0 to 26)
Logic
3
Reg File
RA
Bit-Read
Counter
5
(0 to 7)
CLK155
CLK1.7
77 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
