VSC6134
Datasheet
2.5
Section Overhead Generator
The following functions are supported by the transmit section overhead (SOH) generator block:
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Framing pattern (A1/A2) generation
AIS-L generation
BIP-8 generation and insertion
J0 insertion
E1/F1 insertion
Scrambling
D1-D3 insertions
Framing and BIP-8 test error insertion
RAM-based overhead insertion of the SOH bytes for reserved and for national use (191 Z0)
The SOH generator I/O is shown in the following table.
Table 10. SOH Generator Block I/O Description
Name
Direction
Function
RESETN
IN
IN
IN
IN
Active low reset.
CLK
155 MHz system clock.
Global Line and Section Terminator mode selection.
SDH_SL_MODE
TX_DATAI[63:0]
155 Mbps input data bus. DATAI is clocked in on the rising edge of CLK.
Bit 63 is the MSB.
TX_SYNCI
TX_DATAO[63:0]
TX_SYNCO
SP_AIS_P
IN
OUT
OUT
IN
Tx active high sync signal coincident with the A1-1 byte of the input
frame.
155 Mbps output data bus. DATAO is clocked out on the rising edge of
CLK. Bit 63 is the MSB.
Tx active high sync signal coincident with the A1-1 byte of the output
frame.
Indicates that an AIS-P indication is being generated by the same path
line overhead generator.
FAILURE
IN
Active high signal indicating that the receive SOH detected either a LOS
or LOF.
ROWCNT[3:0]
COLCNT[6:0]
OUT
OUT
OUT
IN
Tx STS-192/STM-64 frame row counter (rows 0 to 8).
Tx STS-192/STM-64 frame column counter (columns 0 to 89).
Tx STS-192/STM-64 frame set counter (sets 0 to 23).
SETCNT[4:0]
SOHGEN_SELECT
Active high select signal for selecting the SOH generator block.
SOHGEN_RDATA[15:0] should be 0 when SOHGEN_SELECT is low.
CLR_RD_WRN
IN
Control signal indicating whether status registers are cleared on-read or
on-write.
MPU_CLK
IN
IN
IN
Microprocessor clock.
MPU_RESETN
MPU_RDENA
Active low MPU_CLK reset.
Microprocessor read enable signal.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
