VSC6134
Datasheet
Table 14. Rx Serial Overhead Interface Data Ordering (continued)
Cycle Numbers
121-128
129-136
137-144
145-152
153-160
161-168
169-176
177-184
185-192
193-200
201-208
209-216
Description
D11 byte
D12 byte
S1 byte
E2 byte
B1 bit error count
B2 bit error count (most-significant byte)
B2 bit error count (least-significant byte)
B2 block error count (most-significant byte)
B2 block error count (least-significant byte)
M0 byte
M1 byte
Stuff byte (all zeros)
In the LOF, LOS or SEF states, the frame sync (AD/DRRXSDHOHFS) and data signals
(AD/DRRXSDHOHD) are held at 0. The ADSDHOHCLK and DRSDHOHCLK outputs continue to
run as long as RSCLK1 (add path) and TXCLKSCRC1 (drop path) input clocks are provided. The
following table provides the I/O for the overhead extraction block.
Table 15. SONET/SDH Overhead Extraction Block I/O
Name
Direction
Function
RESETN
CLK155
IN
IN
IN
Active low reset.
155-MHz system clock.
DATA[BW-1:0]
155-Mbps input data bus clocked on the rising edge of CLK155. Bit BW-1
is the MSB.
LOSF
SEF
IN
IN
Active high signal indication loss-of-signal or loss-of-frame. Output is
disabled when LOSF is active.
Active high signal indicating severely-errored-frame. Output is disabled
when SEF is active.
SYNC
IN
IN
Rx STS-192/STM-64 frame sync signal.
Active low port reset.
DL17RESETN
DL17CLK
OHEXT_INIT_DONE
RFS
IN
Line clock (divide by 360 of the input 622-MHz clock).
Active high signal indicating that all memory initialization is done.
Received overhead output frame sync signal.
Received overhead output data.
OUT
OUT
OUT
RDATA
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
