VSC6134
Datasheet
The 72 8-bit registers are stored in 36 16-bit registers as shown in the following table.
Table 12. TX DCC Register Arrangement
Register
Register Content
TX_DCC0[15:0]
TX_DCC1[15:0]
TX_DCC2[15:0]
[15:8]: D1 byte for frame #1
[7:0]: D2 byte for frame #1
[15:8]: D3 byte for frame #1
[7:0]: D1 byte for frame #2
[15:8]: D2 byte for frame #2
[7:0]: D3 byte for frame #2
.
.
.
.
.
.
TX_DCC35[15:0]
[15:8]: D2 byte for frame #24
[7:0]: D3 byte for frame #24
2.5.4
2.5.5
E1 and F1 Generator
Two registers, TX_E1[7:0] and TX_F1[7:0], are allocated for the system to program the E1 and F1
bytes. These bytes are then inserted in the corresponding locations in the STM-64/STS-192 frame. Note
that the E1 and F1 bytes insertions may be provisionally disabled using configuration bits E1_SOURCE
and F1_SOURCE.
B1 BIP-8 Generator
BIP-8 even parity code is calculated over the entire bits of the scrambled STS-192/STM-64 frame and
placed in the B1 byte of the following frame before scrambling. Also, when the provisionable
configuration bit BIPERR_INSERT is set to 1, the BIP-8 byte is corrupted (for example, inverted) for
test purposes. Note that the B1 byte insertion may be provisionally disabled using configuration bit
B1_SOURCE.
2.5.6
2.5.7
J0 Generator
Either a 64-byte sequence or a 16-byte SAPI can be inserted in the outgoing J0 byte, depending on the
configuration bit TX_J0CNTRL. If TX_J0CNTRL = 0, the 64-byte sequence is transmitted; otherwise,
a 16-byte sequence is sent. Note that J0 insertion may be provisionally disabled using configuration bit
J0_SOURCE.
Z0 Generator
Reserved or national use bytes (Z0) are stored in the transmit SOH RAM and inserted in the proper
location. Note that the Z0 bytes insertions may be provisionally disabled using configuration bit
Z0_SOURCE.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
