VSC6134
Datasheet
Table 11. Section Overhead Generator Mode Functions
VSC6134 Mode Is Section Terminator
(SONET_SL_MODE = 1)
VSC6134 Mode Is Line Terminator
(SONET_SL_MODE = 0)
In Fail Condition?
(LOS or LOF)
YES
Generate AIS-L— Always regenerate
A1/A2/B1 if AISAUTOENA = 1 or
AISMANUENA = 1. Only regenerate
J0/E1/F1/DCC if provisioned by
respective source configuration bits and
AISAUTOENA = 1 or
If AISMANUENA = 0 and sp_ais_p = 1,
then only regenerate
A1/A2/B1/J0/E1/F1/DCC if provisioned
by respective source configuration bits.
If AISMANUENA = 1, then always
regenerate A1/A2/B1 and only
regenerate E1/F1/J0/DCC if
AISMANUENA = 1.
provisioned by respective source
configuration bits.
NO
If AISMANUENA = 0, then only
regenerate A1/A2/B1/E1/F1/J0/DCC if
provisioned by respective source
configuration bits. If AISMANUENA = 1,
then always regenerate A1/A2/B1 and
only regenerate E1/F1/J0/DCC if
provisioned by respective source
configuration bits.
If AISMANUENA = 0, then only
regenerate A1/A2/B1/E1/F1/J0/DCC if
provisioned by respective source
configuration bits. If
AISMANUENA = 1, then always
regenerate A1/A2/B1 and only
regenerate E1/F1/J0/DCC if
provisioned by respective source
configuration bits.
2.5.3
D1 to D3 (DCC) Generator
Seventy-two 8-bit registers are allocated for storing the value of the D1 to D3 bytes for 24 consecutive
frames (3 ms). These registers are normally updated every 3 ms by the system (D1 to D3 for the
24 consecutive frames must be written in order ending with the D1 to D3 bytes for the 24th frame). The
SOH generator inserts the register contents in the proper D1 to D3 positions for 24 consecutive frames,
at which time an interrupt status bit TX_DCCRDYS bit is set and an interrupt is generated (if the
interrupt mask bit RX_DCCRDYM = 0). The interrupt is an indication to the system that the DCC
registers are ready to be updated with new data. Old data is transmitted in the D1 to D3 positions if
system fails to update the registers. Note that DCC bytes insertions may be provisionally disabled using
configuration bit DCC_SOURCE.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
