VSC6134
Datasheet
2.6
Rx Overhead Transport Extraction Block
Transport overhead bytes are extracted and output using the transport output interface. The interface
consists of a 1.728 MHz output clock (AD/DRSDHOHCLK), an 8 kHz output frame sync
(AD/DRRXSDHOHFS) locked to the STS192 frame reference, and a serial output data signal
(AD/DRRXSDHOHD). The following figure shows the timing relationship between these signals.
Figure 12. Rx Serial Overhead Interface Timing
AD/DRRXSDHOHCLK
AD/DRRXSDHOHFS
LSB of Fixed Stuff
MSB of J0 Byte
AD/DRRXSDHOHD
th
The serial interface 1.728 MHz output clock (AD/DRSDHOHCLK) is 1/90 of the internal device
clock of 155.52 MHz. The data output order follows the SONET frame overhead order where the
overhead bytes are received along with the addition of B1 and B2 parity error information (bit and
block) and one stuff byte, as shown in the following table.
Table 14. Rx Serial Overhead Interface Data Ordering
Cycle Numbers
1-8
Description
J0 byte
9-16
E1 byte
F1 byte
D1 byte
D2 byte
D3 byte
K1 byte
K2 byte
D4 byte
D5 byte
D6 byte
D7 byte
D8 byte
D9 byte
D10 byte
17-24
25-32
33-40
41-48
49-56
57-64
65-72
73-80
81-88
89-96
97-104
105-112
113-120
75 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
