VSC6134
Datasheet
2.4.5
2.4.6
S1 Generator
The S1 byte may be generated from the serial overhead interface or from an internal configuration
register, TX_S1BYTE[7:0]. Configuration bit TX_S1_SOURCE enables the insertion of the S1 byte.
When S1 insertion is disabled, the S1 byte is passed through transparently.
M0 and M1 Generator and Error Insertion
The line remote error indication bytes M1 and M0 are generated from the number of B2 parity errors
received from the opposite path for one STS-192 frame. For STS-192 (ITU-G.707 recommendations),
the maximum number of errors cannot exceed 1536 errors for M0/M1 mode or 255 errors for M1 only
mode. You can select either M0/M1 or M1 mode using configuration bit TX_M0M1_SELECT.
Because the frame rates may be asynchronous between the add and drop paths, the count is accumulated
until insertion. If the accumulation exceeds 1536 errors (255 for M1 mode), 1536 errors (255 for
M1 mode) are sent, and the remainder is rolled over into the next frame. When the remainder is inserted,
the accumulator is cleared.
The M0/M1 and M1 functions are implemented as a 12-bit adder. When the adder exceeds 1536 errors
(255 for M1 mode), 1536 errors (255 for M1 mode) are transmitted in the M0 and M1 bytes, and the
remainder is stored for transmission in the next frame. An M0/M1 error can be introduced by setting
configuration bit TX_M0M1ERR_INSRT to 1. The corrupted M0 and M1 byte values are taken from
configuration register TX_M0M1ERR_REG[15:0]. The M0/M1 error register should not exceed
1536 errors (255 for M1 mode).
2.4.7
2.4.8
E2 Generator
The E2 byte can be inserted either from an internal register, TX_E2BYTE[7:0], or from the serial
overhead interface. Configuration bit TX_E2_SOURCE enables the insertion of the E2 byte. Interrupt
status bit TX_E2RDY_S indicates the previously written E2 byte was inserted into the outgoing frame.
This interrupt status bit may be masked using mask bit TX_E2RDY_M.
Reserve Line Overhead Bytes Insertion
The remaining reserve bytes of the line overhead are inserted as a fixed stuff pattern (0xAA or 0x55)
provisioned by configuration bit TX_RESERV. This stuff pattern is inserted only when line overhead
generation is enabled (TX_LINE_BYPASS = 0) and AIS-P is being generated by the line overhead
generator (that is, when the SP_AIS_L, SP_LOF, SP_LOS, or SP_LOC conditions are detected). When
line overhead generation is disabled, the received reserve line overhead bytes are passed through
transparently.
2.4.9
Line Overhead Bypass
When TX_LINE_BYPASS is set, all bytes of the line overhead and all bytes of the payload are passed
through transparently.
2.4.10
Line Overhead Generator Registers
For information about the registers for the line overhead generator, see “Line Overhead Generator
Registers,” page 245.
69 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
