TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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6. Write Data for the last 40 outputs into TX register
SPI_TX_DATA <= 0xAA5555AA55
7. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
Chain of 10 74xx595 shift registers used as 80 digital outputs (bad example)
This bad example is the same as the previous one but with the non-recommended datagram split of 64
bits + 16 bit. This requires more communication since not only the SPI_CONF register needs to be changed
between the SPI_TX_DATA writes but also the SPI_LENGTH register changes every time.
Configuration and first transmission
1. Use 6.25 MHz SPI clock (25MHz/(4+(2*0))) = (25MHz/4)
SPI_TIME <= 0x00
2. Use a 64 bit datagram
SPI_LENGTH <= 0x3F
3. Start on TX write, SPI-Mode 3, MSB first, Keep CS low, Slave 0)
SPI_CONF <= 0x0068
4. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
5. Write Data for the first 64 outputs into TX register
SPI_TX_DATA <= 0x5555AAAA5555AAAA
6. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
7. Use a 16 bit datagram (remaining outputs)
SPI_LENGTH <= 0x0F
8. Start on TX write, SPI-Mode 3, MSB first, Drive CS high at the end, Slave 0)
SPI_CONF <= 0x0060
9. Write Data for the last 16 outputs into TX register
SPI_TX_DATA <= 0x55AA
10. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
Next transmission with inverted data
1. Use a 64 bit datagram
SPI_LENGTH <= 0x3F
2. Start on TX write, SPI-Mode 3, MSB first, Keep CS low, Slave 0)
SPI_CONF <= 0x0068
3. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
4. Write Data for the first 64 outputs into TX register
SPI_TX_DATA <= 0xAAAA5555AAAA5555
5. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
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