TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
162 / 204
5. Write Data into TX register (e.g. TMC262 DRVCONF register, all 64bit are shown)
SPI_TX_DATA <= 0x00000000000EF010
6. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
7. Read Data from RX register
rxdatagram = SPI_RX_DATA
Chain of 10 74xx595 shift registers used as 80 digital outputs (good example)
This example shows the transmission of a longer datagram, in this case 80 bits that are shifted into a chain
of 74xx595 shift registers. The NCS of the SPI interface can be used as the storage clock of the 74xx595
to transfer the contents of the shift register into the storage register. The data that should be sent is
0x5555AAAA5555AAAA55AA.
It is recommended to split the data into two chunks of 40 bits each: 0x5555AAAA55 and 0x55AAAA55AA.
Configuration and first transmission
1. Use 6.25 MHz SPI clock (25MHz/(4+(2*0))) = (25MHz/4)
SPI_TIME <= 0x00
2. Use a 40 bit datagram
SPI_LENGTH <= 0x28
3. Start on TX write, SPI-Mode 3, MSB first, Keep CS low, Slave 0)
SPI_CONF <= 0x0068
4. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
5. Write Data for the first 64 outputs into TX register
SPI_TX_DATA <= 0x5555AAAA55
6. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
7. Start on TX write, SPI-Mode 3, MSB first, Drive CS high at the end, Slave 0)
SPI_CONF <= 0x0060
8. Write Data for the last 16 outputs into TX register
SPI_TX_DATA <= 0x55AAAA55AA
9. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
Next transmission with inverted data
1. Start on TX write, SPI-Mode 3, MSB first, Keep CS low, Slave 0)
SPI_CONF <= 0x0068
2. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
3. Write Data for the first 40 outputs into TX register
SPI_TX_DATA <= 0xAAAA5555AA
4. Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
5. Start on TX write, SPI-Mode 3, MSB first, Drive CS high at the end, Slave 0)
SPI_CONF <= 0x0060
©2018 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany
Terms of delivery and rights to technical change reserved.
Download newest version at www.trinamic.com
TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
