TPS929160-Q1
ZHCSNG0 – APRIL 2023
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表 7-59. PWMLH0 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
PWMLOWOUTH0
R
0h
Reserved
R/W
0h
4-LSB output PWM duty-cycle setting for OUTH0
7.6.1.40 PWMLH1 Register (Offset = 2Fh) [Reset = 00h]
PWMLH1 is shown in 图 7-60 and described in 表 7-60.
Return to the Summary Table.
图 7-60. PWMLH1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTH1
R/W-0h
表 7-60. PWMLH1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTH1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTH1
7.6.1.41 PWMLR0 Register (Offset = 30h) [Reset = 00h]
PWMLR0 is shown in 图 7-61 and described in 表 7-61.
Return to the Summary Table.
图 7-61. PWMLR0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
表 7-61. PWMLR0 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.42 PWMLR1 Register (Offset = 31h) [Reset = 00h]
PWMLR1 is shown in 图 7-62 and described in 表 7-62.
Return to the Summary Table.
图 7-62. PWMLR1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
表 7-62. PWMLR1 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
72
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