TPS929160-Q1
ZHCSNG0 – APRIL 2023
www.ti.com.cn
图 7-53. PWMLE0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTE0
R/W-0h
表 7-53. PWMLE0 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
PWMLOWOUTE0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTE0
7.6.1.34 PWMLE1 Register (Offset = 29h) [Reset = 00h]
PWMLE1 is shown in 图 7-54 and described in 表 7-54.
Return to the Summary Table.
图 7-54. PWMLE1 Register
7
6
5
4
3
2
1
0
0
0
RESERVED
R-0h
PWMLOWOUTE1
R/W-0h
表 7-54. PWMLE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTE1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTE1
7.6.1.35 PWMLF0 Register (Offset = 2Ah) [Reset = 00h]
PWMLF0 is shown in 图 7-55 and described in 表 7-55.
Return to the Summary Table.
图 7-55. PWMLF0 Register
7
6
5
4
3
2
1
RESERVED
R-0h
PWMLOWOUTF0
R/W-0h
表 7-55. PWMLF0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTF0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTF0
7.6.1.36 PWMLF1 Register (Offset = 2Bh) [Reset = 00h]
PWMLF1 is shown in 图 7-56 and described in 表 7-56.
Return to the Summary Table.
图 7-56. PWMLF1 Register
7
6
5
4
3
2
1
RESERVED
R-0h
PWMLOWOUTF1
R/W-0h
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
70
Submit Document Feedback
Product Folder Links: TPS929160-Q1
TI [ TEXAS INSTRUMENTS ]
