TPS929160-Q1
ZHCSNG0 – APRIL 2023
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表 7-46. PWMLA1 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
PWMLOWOUTA1
R
0h
Reserved
R/W
0h
4-LSB output PWM duty-cycle setting for OUTA1
7.6.1.27 PWMLB0 Register (Offset = 22h) [Reset = 00h]
PWMLB0 is shown in 图 7-47 and described in 表 7-47.
Return to the Summary Table.
图 7-47. PWMLB0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTB0
R/W-0h
表 7-47. PWMLB0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTB0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTB0
7.6.1.28 PWMLB1 Register (Offset = 23h) [Reset = 00h]
PWMLB1 is shown in 图 7-48 and described in 表 7-48.
Return to the Summary Table.
图 7-48. PWMLB1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTB1
R/W-0h
表 7-48. PWMLB1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTB1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTB1
7.6.1.29 PWMLC0 Register (Offset = 24h) [Reset = 00h]
PWMLC0 is shown in 图 7-49 and described in 表 7-49.
Return to the Summary Table.
图 7-49. PWMLC0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTC0
R/W-0h
表 7-49. PWMLC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTC0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTC0
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
68
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