TPS929160-Q1
ZHCSNG0 – APRIL 2023
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图 7-66. PWMLR5 Register (continued)
R-0h
表 7-66. PWMLR5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RESERVED
R
0h
Reserved
7.6.1.47 PWMLR6 Register (Offset = 36h) [Reset = 00h]
PWMLR6 is shown in 图 7-67 and described in 表 7-67.
Return to the Summary Table.
图 7-67. PWMLR6 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
表 7-67. PWMLR6 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.48 PWMLR7 Register (Offset = 37h) [Reset = 00h]
PWMLR7 is shown in 图 7-68 and described in 表 7-68.
Return to the Summary Table.
图 7-68. PWMLR7 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
表 7-68. PWMLR7 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.49 OUTEN0 Register (Offset = 40h) [Reset = 00h]
OUTEN0 is shown in 图 7-69 and described in 表 7-69.
Return to the Summary Table.
图 7-69. OUTEN0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
ENOUTB1
R/W-0h
ENOUTB0
R/W-0h
RESERVED
R-0h
ENOUTA1
R/W-0h
ENOUTA0
R/W-0h
表 7-69. OUTEN0 Register Field Descriptions
Bit
7-6
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
74
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