TPS929160-Q1
ZHCSNG0 – APRIL 2023
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7.6.1.43 PWMLR2 Register (Offset = 32h) [Reset = 00h]
PWMLR2 is shown in 图 7-63 and described in 表 7-63.
Return to the Summary Table.
图 7-63. PWMLR2 Register
7
6
5
4
3
2
1
1
1
1
0
0
0
0
RESERVED
R-0h
表 7-63. PWMLR2 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.44 PWMLR3 Register (Offset = 33h) [Reset = 00h]
PWMLR3 is shown in 图 7-64 and described in 表 7-64.
Return to the Summary Table.
图 7-64. PWMLR3 Register
7
6
5
4
3
2
RESERVED
R-0h
表 7-64. PWMLR3 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.45 PWMLR4 Register (Offset = 34h) [Reset = 00h]
PWMLR4 is shown in 图 7-65 and described in 表 7-65.
Return to the Summary Table.
图 7-65. PWMLR4 Register
7
6
5
4
3
2
RESERVED
R-0h
表 7-65. PWMLR4 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.46 PWMLR5 Register (Offset = 35h) [Reset = 00h]
PWMLR5 is shown in 图 7-66 and described in 表 7-66.
Return to the Summary Table.
图 7-66. PWMLR5 Register
7
6
5
4
3
2
RESERVED
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Product Folder Links: TPS929160-Q1
English Data Sheet: SLVSG60
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