TPS929160-Q1
ZHCSNG0 – APRIL 2023
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图 7-56. PWMLF1 Register (continued)
表 7-56. PWMLF1 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
PWMLOWOUTF1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTF1
7.6.1.37 PWMLG0 Register (Offset = 2Ch) [Reset = 00h]
PWMLG0 is shown in 图 7-57 and described in 表 7-57.
Return to the Summary Table.
图 7-57. PWMLG0 Register
7
6
5
4
3
2
1
0
0
0
RESERVED
R-0h
PWMLOWOUTG0
R/W-0h
表 7-57. PWMLG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTG0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTG0
7.6.1.38 PWMLG1 Register (Offset = 2Dh) [Reset = 00h]
PWMLG1 is shown in 图 7-58 and described in 表 7-58.
Return to the Summary Table.
图 7-58. PWMLG1 Register
7
6
5
4
3
2
1
RESERVED
R-0h
PWMLOWOUTG1
R/W-0h
表 7-58. PWMLG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTG1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTG1
7.6.1.39 PWMLH0 Register (Offset = 2Eh) [Reset = 00h]
PWMLH0 is shown in 图 7-59 and described in 表 7-59.
Return to the Summary Table.
图 7-59. PWMLH0 Register
7
6
5
4
3
2
1
RESERVED
R-0h
PWMLOWOUTH0
R/W-0h
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Product Folder Links: TPS929160-Q1
English Data Sheet: SLVSG60
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