TPS929160-Q1
ZHCSNG0 – APRIL 2023
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表 7-39. PWMMR2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RESERVED
R
0h
Reserved
7.6.1.20 PWMMR3 Register (Offset = 13h) [Reset = 00h]
PWMMR3 is shown in 图 7-40 and described in 表 7-40.
Return to the Summary Table.
图 7-40. PWMMR3 Register
7
6
5
4
3
2
1
1
1
0
RESERVED
R-0h
表 7-40. PWMMR3 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.21 PWMMR4 Register (Offset = 14h) [Reset = 00h]
PWMMR4 is shown in 图 7-41 and described in 表 7-41.
Return to the Summary Table.
图 7-41. PWMMR4 Register
7
6
5
4
3
2
0
RESERVED
R-0h
表 7-41. PWMMR4 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.22 PWMMR5 Register (Offset = 15h) [Reset = 00h]
PWMMR5 is shown in 图 7-42 and described in 表 7-42.
Return to the Summary Table.
图 7-42. PWMMR5 Register
7
6
5
4
3
2
0
RESERVED
R-0h
表 7-42. PWMMR5 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.23 PWMMR6 Register (Offset = 16h) [Reset = 00h]
PWMMR6 is shown in 图 7-43 and described in 表 7-43.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
66
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