TPS929160-Q1
ZHCSNG0 – APRIL 2023
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图 7-36. PWMMH1 Register
7
6
5
4
3
2
1
0
PWMOUTH1
R/W-0h
表 7-36. PWMMH1 Register Field Descriptions
Bit
7-0
Field
PWMOUTH1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTH1
7.6.1.17 PWMMR0 Register (Offset = 10h) [Reset = 00h]
PWMMR0 is shown in 图 7-37 and described in 表 7-37.
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图 7-37. PWMMR0 Register
7
6
5
4
3
2
1
1
1
0
0
0
RESERVED
R-0h
表 7-37. PWMMR0 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.18 PWMMR1 Register (Offset = 11h) [Reset = 00h]
PWMMR1 is shown in 图 7-38 and described in 表 7-38.
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图 7-38. PWMMR1 Register
7
6
5
4
3
2
RESERVED
R-0h
表 7-38. PWMMR1 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.19 PWMMR2 Register (Offset = 12h) [Reset = 00h]
PWMMR2 is shown in 图 7-39 and described in 表 7-39.
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图 7-39. PWMMR2 Register
7
6
5
4
3
2
RESERVED
R-0h
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Product Folder Links: TPS929160-Q1
English Data Sheet: SLVSG60
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