TPS929160-Q1
ZHCSNG0 – APRIL 2023
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表 7-32. PWMMF1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PWMOUTF1
R/W
0h
8-MSB output PWM duty-cycle setting for OUTF1
7.6.1.13 PWMMG0 Register (Offset = Ch) [Reset = 00h]
PWMMG0 is shown in 图 7-33 and described in 表 7-33.
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图 7-33. PWMMG0 Register
7
6
5
4
3
2
1
0
PWMOUTG0
R/W-0h
表 7-33. PWMMG0 Register Field Descriptions
Bit
7-0
Field
PWMOUTG0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTG0
7.6.1.14 PWMMG1 Register (Offset = Dh) [Reset = 00h]
PWMMG1 is shown in 图 7-34 and described in 表 7-34.
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图 7-34. PWMMG1 Register
7
6
5
4
3
2
1
0
PWMOUTG1
R/W-0h
表 7-34. PWMMG1 Register Field Descriptions
Bit
7-0
Field
PWMOUTG1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTG1
7.6.1.15 PWMMH0 Register (Offset = Eh) [Reset = 00h]
PWMMH0 is shown in 图 7-35 and described in 表 7-35.
Return to the Summary Table.
图 7-35. PWMMH0 Register
7
6
5
4
3
2
1
0
PWMOUTH0
R/W-0h
表 7-35. PWMMH0 Register Field Descriptions
Bit
7-0
Field
PWMOUTH0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTH0
7.6.1.16 PWMMH1 Register (Offset = Fh) [Reset = 00h]
PWMMH1 is shown in 图 7-36 and described in 表 7-36.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
64
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