TPS929160-Q1
ZHCSNG0 – APRIL 2023
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表 7-25. PWMMC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PWMOUTC0
R/W
0h
8-MSB output PWM duty-cycle setting for OUTC0
7.6.1.6 PWMMC1 Register (Offset = 5h) [Reset = 00h]
PWMMC1 is shown in 图 7-26 and described in 表 7-26.
Return to the Summary Table.
图 7-26. PWMMC1 Register
7
6
5
4
3
2
1
0
PWMOUTC1
R/W-0h
表 7-26. PWMMC1 Register Field Descriptions
Bit
7-0
Field
PWMOUTC1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTC1
7.6.1.7 PWMMD0 Register (Offset = 6h) [Reset = 00h]
PWMMD0 is shown in 图 7-27 and described in 表 7-27.
Return to the Summary Table.
图 7-27. PWMMD0 Register
7
6
5
4
3
2
1
0
PWMOUTD0
R/W-0h
表 7-27. PWMMD0 Register Field Descriptions
Bit
7-0
Field
PWMOUTD0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTD0
7.6.1.8 PWMMD1 Register (Offset = 7h) [Reset = 00h]
PWMMD1 is shown in 图 7-28 and described in 表 7-28.
Return to the Summary Table.
图 7-28. PWMMD1 Register
7
6
5
4
3
2
1
0
PWMOUTD1
R/W-0h
表 7-28. PWMMD1 Register Field Descriptions
Bit
7-0
Field
PWMOUTD1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTD1
7.6.1.9 PWMME0 Register (Offset = 8h) [Reset = 00h]
PWMME0 is shown in 图 7-29 and described in 表 7-29.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
62
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