TPS929160-Q1
ZHCSNG0 – APRIL 2023
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图 7-22. PWMMA1 Register
7
6
5
4
3
2
1
0
PWMOUTA1
R/W-0h
表 7-22. PWMMA1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PWMOUTA1
R/W
0h
8-MSB output PWM duty-cycle setting for OUTA1
7.6.1.3 PWMMB0 Register (Offset = 2h) [Reset = 00h]
PWMMB0 is shown in 图 7-23 and described in 表 7-23.
Return to the Summary Table.
图 7-23. PWMMB0 Register
7
6
5
4
3
2
1
0
PWMOUTB0
R/W-0h
表 7-23. PWMMB0 Register Field Descriptions
Bit
7-0
Field
PWMOUTB0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTB0
7.6.1.4 PWMMB1 Register (Offset = 3h) [Reset = 00h]
PWMMB1 is shown in 图 7-24 and described in 表 7-24.
Return to the Summary Table.
图 7-24. PWMMB1 Register
7
6
5
4
3
2
1
0
PWMOUTB1
R/W-0h
表 7-24. PWMMB1 Register Field Descriptions
Bit
7-0
Field
PWMOUTB1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTB1
7.6.1.5 PWMMC0 Register (Offset = 4h) [Reset = 00h]
PWMMC0 is shown in 图 7-25 and described in 表 7-25.
Return to the Summary Table.
图 7-25. PWMMC0 Register
7
6
5
4
3
2
1
0
PWMOUTC0
R/W-0h
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Product Folder Links: TPS929160-Q1
English Data Sheet: SLVSG60
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