TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
5 C64x+ Megamodule
5.1 Megamodule Diagram
The C64x+ Megamodule consists of several components - the C64x+ CPU and associated C64x+
Megamodule core, level-one and level-two memories (L1P, L1D, L2), RSA accelerator, data trace
formatter (DTF), embedded trace buffer (ETB), the interrupt controller, power-down controller, external
memory controller and a dedicated power/sleep controller (LPSC). The C64x+ Megamodule also provides
support for memory protection and bandwidth management (for resources local to the C64x+
Megamodule). Figure 5-1 provides a block diagram of the C64x+ Megamodule.
32KB L1P
Memory Controller (PMC) with
Memory Protect/Bandwidth Mgmt
C64x+ DSP Core
L2 Cache/
Instruction Fetch
SRAM
16-/32-bit Instruction Dispatch
512, 1024, or
1536 KB
Control Registers
In-Circuit Emulation
Boot
Instruction Decode
Controller
Data Path A
Data Path B
A Register File
B Register File
PLLC
LPSC
GPSC
A31 - A16
A15 - A0
B31 - B16
B15 - B0
DMA Switch
Fabric
.M1
.M2
.L1
.S1
xx
xx
.D1
.D2
xx
xx
.S2
.L2
Data Memory Controller (DMC) with
Memory Protect/Bandwidth Mgmt
CFG Switch
Fabric
32KB L1D
RSA
RSA
Figure 5-1. C64x+ Megamodule Block Diagram
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C64x+ Megamodule
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