TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
ETB/DTF
(3)
Bridge
20
S
M
M
S
S
TCP
VCP
3
Semaphore
FSYNC
S
S
S
S
CFGC/CIC
GPIO
C64x+
McBSPs
(2)
S
Megamodule
Core 0
M
S
2
S
S
I2C
Bridge
15
M
GPSC
C64x+
Megamodule
Core 1
M
M
S
S
PLL Ctrls
(2)
2
S
SCR D
32-bit
VBUSP
T
i
C64x+
Megamodule
Core 2
S
S
TPMGR
M
S
AIF
6
m
e
r
Timer64s
(6)
RapidIO
S
S
SCR G
32-bit
VBUSP
M
M
M
RapidIO
CPPI
SCR B
(see
S
S
MDIO
M
S
Figure 4-1)
CP-GMAC
S
S
FEI
BEI
Ethernet
CPPI
E
M
A
C
R
A
C
S
Bridge
14
2
GCCPs
(2)
SGMII
S
S
S
Wrapper
EMIC
E
D
M
A
3
6
TPTCs
(6)
Bridge
13
S
S
SCR E
32-bit
VBUSP
TPCC
M
Figure 4-2. Configuration Switched Central Resource Block Diagram
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System Interconnect
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