TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
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4.4 Priority Allocation
On the TCI6487/8 device, each of the masters is assigned a priority via the Priority Allocation Register
(PRI_ALLOC), see Figure 4-3. User-programmable priority registers allow software configuration of the
data traffic through the SCR. The priority is enforced when several masters in the system vie for the same
endpoint. The PRI value of 000b has the highest priority, while the PRI value 111b has the lowest priority.
A chip-level register must be provided to set these values for masters that do not have their own register
internally.
The configuration SCR port on the data SCR is considered a single endpoint meaning priority will be
enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the
configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the
C64x+ Megamodule.
The 4-Byte PRI_ALLOC register address range is 0288 083C - 0288 083F.
31
6 5
3 2
0
Reserved
RapidIO CPPI
RW +001
EMAC
RW, +00 0000 0000 0000 0000 0000 0000
RW, +001
Figure 4-3. Priority Allocation Register (PRI_ALLOC)
All other master peripherals are not present in the PRI_ALLOC register, as they have their own registers
to program their priorities and do not need a default priority setting. For more information on the default
priority values in these peripheral registers, see the device-compatible peripheral reference guides. TI
recommends that these priority registers be reprogrammed upon initial use.
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System Interconnect
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