TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
4.2 Data Switch Fabric Connections
Figure 4-1 shows the DMA switch fabric, including the EDMA3, connection between slaves and masters
through the data switched central resource (SCR). Masters are shown on the right and slaves on the left.
Chip events
Channel
Controller
(CC)
64 channels
SCR B
64-bit
VBUSM
64
M
M
S
S
Transfer
Controller
(TC)
x3
x3
64
64
64
64
32
64
64
64
Bridge
28
Bridge
12
M
M
M
S
S
S
S
TCP
VCP
3 channels
64
Bridge
29
Bridge
11
32
32
64
Bridge
6
Bridge
M
M
M
M
S
S
S
S
S
S
S
S
S
EMAC
7
SCRD
(CFG)
Bridge
10
64
128
BridgMe
25
RapidIO
32
32
MCBSPs
(2)
32
32
64
32
Bridge
64
RapidIO
CPPI
Bridge
16
Bridge
17
M
32
9
64
64
RAC Back-
End 1
Bridge
18
S
ROM
64
C64x+
Megamodule M
Core 1
64
DDR2
EMIF
M
M
S
S
C64x+
64
64
64
64
Megamodule M
Core 2
Bridge
27
RAC Front-
End
C64x+
Megamodule M
Core 3
M
M
64
64
Bridge
5
Bridge
4
128
128
64
64
SCR A
128-bit
VBUSM
128
128
Bridge
S
3
M
M
M
Bridge
2
S
S
Bridge
23
S
S
AIF Read
AIF Write
128
M
128
Bridge
22
Bridge
24
Transfer
Controller
(TC)
x6
x6
128
128
128
C64x+
Megamodule
Core 1
3 channels
128
S
M
M
M
M
S
S
C64x+
Megamodule
Core 2
128
128
RAC Back-
M
End 0
Bridge
1
S
S
C64x+
Megamodule
Core 3
Figure 4-1. Switched Central Resource Block Diagram
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System Interconnect
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