TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.7.4 PLL1 Controller Input and Output Electrical Data/Timing
Table 8-31. Timing Requirements for SYSCLK and ALTCORECLK(1)
(see Figure 8-21)
NO.
PARAMETERS
AIF Used, CORECLKSEL=0
Cycle time, SYSCLK(N|P)
MIN
MAX UNIT
1
2
3
4
5
tc(SYSCLK)
tw(SYSCLKH)
tw(SYSCLKL)
tt(SYSCLK)
tj(SYSCLK)
16.276
0.4C
0.4C
50
16.276
ns
ns
ns
ps
ps
Pulse duration, SYSCLK(N|P) high
Pulse duration, SYSCLK(N|P) low
Transition time, SYSCLK(N|P)
1300
4
Period Jitter (RMS), SYSCLK(N|P)
AIF Used, CORECLKSEL=1
1
2
3
4
5
tc(SYSCLK)
tw(SYSCLKH)
tw(SYSCLKL)
tt(SYSCLK)
tj(SYSCLK)
Cycle time, SYSCLK(N|P)
6.51
0.4C
0.4C
50
16.276
ns
ns
ns
ps
ps
Pulse duration, SYSCLK(N|P) high
Pulse duration, SYSCLK(N|P) low
Transition time, SYSCLK(N|P)
1300
4
Period Jitter (peak-to-peak), SYSCLK(N|P)
CORECLKSEL=1
1
2
3
4
5
tc(ALTCORECLK)
tw(ALTCORECLK)
tw(ALTCORECLKL)
tt(ALTCORECLK)
tj(ALTCORECLK)
Cycle time, ALTCORECLK(N|P)
Pulse duration, ALTCORECLK(N|P) high
Pulse duration, ALTCORECLK(N|P) low
Transition time, ALTCORECLK(N|P)
Period Jitter (peak-to-peak), ALTCORECLK(N|P)
SYSCLKOUT
16
0.4C
0.4C
50
25.00
ns
ns
ns
ps
ps
1300
100
1
2
3
4
tc(CKO)
Cycle time, SYSCLKOUT
10C
4C - 0.7
4C - 0.7
32C
32C + 0.7
32C + 0.7
1
ns
ns
ns
ns
tw(CKOH)
tw(CKOL)
tt(CKO)
Pulse duration, SYSCLKOUT high
Pulse duration, SYSCLKOUT low
Transition time, SYSCLKOUT
(1) If CORECLKSEL = 0, C = 1/SYSCLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency, in ns.
1
4
2
CLKIN
3
4
Figure 8-21. CLKIN Timing
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Peripheral Information and Electrical Specifications
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