TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.7.3.9 PLLDIV Divider Ratio Change Status Register
Whenever a different ratio is written to the PLLDIVn registers, the PLLCTRL flags the change in the
PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only
change the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be
automatically aligned to other clocks. The PLLDIV divider ratio change status register is shown in
Figure 8-19 and described in Table 8-29.
31
15
16
Reserved
R-0
13
12
11
Rsvd
R-0
10
9
0
Reserved
R-0
SYS13
R/W-0
SYS11
R/W-0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-19. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029A 0144]
Table 8-29. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
Field
Value Description
31:13 Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
12
SYS13
Identifies when the SYSCLK13 divide ratio has been modified.
0
1
0
SYSCLK13 ratio has not been modified. When GOSET is set, SYSCLK13 will not be affected.
SYSCLK13 ratio has been modified. When GOSET is set, SYSCLK13 will change to the new ratio.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Identifies when the SYSCLK11 divide ratio has been modified.
11
10
Reserved
SYS11
0
1
0
SYSCLK11 ratio has not been modified. When GOSET is set, SYSCLK11 will not be affected.
SYSCLK11 ratio has been modified. When GOSET is set, SYSCLK11 will change to the new ratio.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
2:0
Reserved
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Peripheral Information and Electrical Specifications
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