TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
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8.7.3.8 PLL Controller Clock Align Control Register
The PLL controller clock align control register (ALNCTL) is shown in Figure 8-18 and described in
Table 8-28.
31
16
Reserved
R-0
15
14
13
Rsvd ALN13 Rsvd ALN11
R-1 R-1 R-1 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
12
11
10
9
0
Reserved
R-0
Reserved
R-1
Figure 8-18. PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029A 0140]
Table 8-28. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit
Field
Value Description
31:14 Reserved
0
1
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
13
12
Reserved
ALN13
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
SYSCLK13 alignment. Do not change the default values of these fields.
0
1
1
Do not align SYSCLK13 to other SYSCLKs during GO operation. If SYS13 in DCHANGE is set to
1, SYSCLK13 switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
Align SYSCLK13 to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set.
The SYSCLK13 ratio is set to the ratio programmed in the RATIO bit in PLLDIV13.
11
10
Reserved
ALN11
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
SYSCLK11 alignment. Do not change the default values of these fields.
0
1
1
Do not align SYSCLK11 to other SYSCLKs during GO operation. If SYS11 in DCHANGE is set to
1, SYSCLK11 switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
Align SYSCLK11 to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set.
The SYSCLK11 ratio is set to the ratio programmed in the RATIO bit in PLLDIV11.
9:0
Reserved
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
124
Peripheral Information and Electrical Specifications
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