TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.7.3.7 PLL Controller Status Register
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in
Figure 8-17 and described in Table 8-27.
31
16
Reserved
R-0
15
1
0
Reserved
R-0
GOSTAT
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-17. PLL Controller Status Register (PLLSTAT) [Hex Address: 029A 013C]
Table 8-27. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
31:1
0
Field
Value Description
Reserved
GOSTAT
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
GO operation status.
0
1
GO operation is not in progress. SYSCLK divide ratios are not being changed.
GO operation is in progress. SYSCLK divide ratios are being changed.
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Peripheral Information and Electrical Specifications
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