TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.9.2 DDR2 Memory Controller Peripheral Register Description(s)
The memory map of the DDR2 controller is shown in Table 8-34.
Table 8-34. DDR2 Memory Controller Registers
HEX ADDRESS
7000 0000
ACRONYM
REGISTER NAME
DDR2 Memory Controller Module and Revision Register
DDR2 Memory Controller Status Register
DDR2 Memory Controller SDRAM Configuration Register
DDR2 Memory Controller SDRAM Refresh Control Register
DDR2 Memory Controller SDRAM Timing 1 Register
DDR2 Memory Controller SDRAM Timing 2 Register
Reserved
MIDR
7000 0004
DMCSTAT
7000 0008
SDCFG
7000 000C
SDRFC
7000 0010
SDTIM1
7000 0014
SDTIM2
7000 0018
-
7000 0020
BPRIO
DDR2 Memory Controller Burst Priority Register
Reserved
7000 0024 - 7000 004C
7000 0050 - 7000 0078
7000 007C - 7000 00BC
7000 00C0 - 7000 00E0
7000 00E4
-
-
Reserved
-
Reserved
-
Reserved
DMCCTL
-
DDR2 Memory Controller Control Register
Reserved
7000 00E8 - 7000 00EC
7000 00F0
DDR2IO
Control Register
DDR2 ODT control register is at 0x7000 00F0
Bits 1:0 are the ODT status, these bits are Read/Write
00 no termination
01 half termination
11 full termination
7000 00F4 - 7000 00FC
7000 0100 - 7FFF FFFF
-
-
Reserved
Reserved
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Peripheral Information and Electrical Specifications
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