TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
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8.7.3.6 PLL Controller Command Register
The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is
shown in Figure 8-16 and described in Table 8-26.
31
15
16
Reserved
R-0
2
1
0
Reserved
R-0
Rsvd
R/W-0
GOSET
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-16. PLL Controller Command Register (PLLCMD) [Hex Address: 029A 0138]
Table 8-26. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31:2
1
Field
Value Description
Reserved
Reserved
GOSET
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0
GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1
to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous
GO operations have completed.
0
1
No effect. Write of 0 clears bit to 0.
Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further
writes of 1 can initiate the GO operation.
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Peripheral Information and Electrical Specifications
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