TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.7.3.5 PLL Controller Divider 13 Register
The PLL controller divider 13 register (PLLDIV13) is shown in Figure 8-15 and described in Table 8-25.
31
16
Reserved
R-0
15
14
5
4
0
D13EN
R/W-1
Reserved
R-0
RATIO
R/W-3
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-15. PLL Controller Divider 13 Register (PLLDIV13) [Hex Address: 029A 0184]
Table 8-25. PLL Controller Divider 13 Register (PLLDIV13) Field Descriptions
Bit
Field
Value
Description
31:16 Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
15
D13EN
Divider 13 enable bit.
0
1
0
Divider 13 is disabled. No clock output.
Divider 13 is enabled.
14:5
4:0
Reserved
RATIO
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
0-1Fh
0h-31h
32h-1Fh
Divider ratio bits.
÷1 to ÷32. Divide frequency by 1 to divide frequency by 32.
Reserved, do not use.
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Peripheral Information and Electrical Specifications
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