TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.7.3.3 PLL Pre-Divider Control Register
The PLL pre-divider control register (PREDIV) is shown in Figure 8-13 and described in Table 8-23.
31
16
Reserved
R-0
15
14
5
4
0
PREDEN
R/W-1
Reserved
R-0
RATIO
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-13. PLL Pre-Divider Control Register (PREDIV) [Hex Address: 029A 0114]
Table 8-23. PLL Pre-Divider Control Register (PREDIV) Field Descriptions
Bit
Field
Value Description
31:16 Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
15
PREDEN
Pre-divider enable bit.
0
1
0
Pre-divider is disabled. No clock output.
Pre-divider is enabled.
14:5
4:0
Reserved
RATIO
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider ratio bits.
0h
1h
2h
÷1. Divide frequency by 1.
÷2. Divide frequency by 2.
÷3. Divide frequency by 3.
3h-1Fh Reserved, do not use.
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Peripheral Information and Electrical Specifications
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