TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
www.ti.com
8.7.3.2 PLL Multiplier Control Register
The PLL multiplier control register (PLLM) is shown in Figure 8-12 and described in Table 8-22. The PLLM
register defines the input reference clock frequency multiplier in conjunction with the PLL divider ratio bits
(RATIO) in the PLL controller pre-divider register (PREDIV).
31
15
16
Reserved
R-0
5
4
0
Reserved
R-0
PLLM
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-12. PLL Multiplier Control Register (PLLM) [Hex Address: 029A 0110]
Table 8-22. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit
31:5
4:0
Field
Value Description
Reserved
PLLM
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLL multiplier bits. Defines the frequency multiplier of the input reference clock in conjunction with
the PLL divider ratio bits (RATIO) in PREDIV.
0h
Eh
x1 multiplier rate
x15 multiplier rate
x20 multiplier rate
x25 multiplier rate
x30 multiplier rate
x32 multiplier rate
13h
18h
1Dh
1Fh
118
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
TI [ TEXAS INSTRUMENTS ]
