TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.7.3 PLL1 Controller Register Descriptions
This section provides a description of the PLL1 controller registers. For details on the operation of the PLL
controller module, see the TMS320TCI6488 DSP Software-Programmable Phase-Locked Loop (PLL)
Controller User's Guide (literature number SPRUEF1).
NOTE: The PLL1 controller registers can only be accessed using the CPU or the emulator.
Not all of the registers documented in the TMS320TCI6488 DSP Software-Programmable Phase-Locked
Loop (PLL) Controller User's Guide (literature number SPRUEF1) are supported on the
TMS320TCI6487/8. Only those registers documented in this section are supported. Furthermore, only the
bits within the registers described here are supported. You should not write to any reserved memory
location or change the value of reserved bits.
8.7.3.1 PLL1 Control Register
The PLL control register (PLLCTL) is shown in Figure 8-11 and described in Table 8-21.
31
16
Reserved
R-0
15
8
7
6
5
4
3
2
1
0
PLL
PWRDN
Reserved
R-0
Rsvd
Rsvd
R-1
Reserved
R/W-0
PLLRST
R/W-1
Rsvd
R-0
PLLEN
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-11. PLL1 Control Register (PLLCTL) [Hex Address: 029A 0100]
Table 8-21. PLL1 Control Register (PLLCTL) Field Descriptions
Bit
31:8
7
Field
Value Description
Reserved
Reserved
Reserved
Reserved
PLLRST
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Reserved. Writes to this register must keep this bit as 0.
6
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
5:4
3
Reserved. Writes to this register must keep this bit as 0.
PLL reset bit
0
1
PLL reset is released
PLL reset is asserted
2
1
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLLPWRDN
PLL power-down mode select bit
0
1
PLL is operational
PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off
PLL enable bit
0
PLLEN
0
1
Bypass mode. Divider PREDIV and PLL are bypassed. All the system clocks (SYSCLKn) are
divided down directly from input reference clock.
PLL mode. Divider PREDIV and PLL are not bypassed. PLL output path is enabled. All the system
clocks (SYSCLKn) are divided down from PLL output.
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Peripheral Information and Electrical Specifications
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