TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
www.ti.com
8.7.2 PLL1 Controller Memory Map
The memory map of the PLL1 controller is shown in Table 8-20. Note that only registers documented here
are accessible on the device. Other addresses in the PLL1 controller memory map should not be modified.
Table 8-20. PLL1 Controller Registers (Including Reset Controller)
HEX ADDRESS
029A 0000 - 029A 00E3
029A 00E4
029A 00E8 - 029A 00FF
029A 0100
029A 0104
029A 0108
029A 010C
029A 0110
029A 0114
029A 0118
029A 011C
029A 0120
029A 0124
029A 0128
029A 012C
029A 0130
029A 0134
029A 0138
029A 013C
029A 0140
029A 0144
029A 0148
029A 014C
029A 0150
029A 0154
029A 0158
029A 015C
029A 0160
029A 0164
029A 0168
029A 016C
029A 0170
029A 0174
029A 0178
029A 017C
029A 0180
029A 0184
029A 0188
029A 018C
ACRONYM
REGISTER NAME
-
Reserved
RSTYPE
Reset Type Status Register (Reset Controller)
-
Reserved
PLLCTL
PLL Control Register
-
Reserved
-
Reserved
-
Reserved
PLLM
PLL Multiplier Control Register
PREDIV
PLL Pre-Divider Control Register
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
PLLCMD
PLL Controller Command Register
PLLSTAT
PLL Controller Status Register
ALNCTL
PLL Controller Clock Align Control Register
DCHANGE
PLLDIV Ratio Change Status Register
-
Reserved
-
Reserved
SYSTAT
SYSCLK Status Register
Reserved
-
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
PLLDIV11
PLL Controller Divider 11 Register
Reserved
-
PLLDIV13
PLL Controller Divider 13 Register
Reserved
-
-
Reserved
116
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
TI [ TEXAS INSTRUMENTS ]
