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SPRS174S – APRIL 2001 – REVISED MARCH 2011
List of Figures
2-1
2-2
2-3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View)
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TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP (Top View)
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Functional Block Diagram
.......................................................................................................
F2812/C2812 Memory Map
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F2811/C2811 Memory Map
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F2810/C2810 Memory Map
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External Interface Block Diagram
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Interrupt Sources
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Multiplexing of Interrupts Using the PIE Block
...............................................................................
Clock and Reset Domains
......................................................................................................
OSC and PLL Block
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Recommended Crystal/Clock Connection
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Watchdog Module
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CPU-Timers
.......................................................................................................................
CPU-Timer Interrupts Signals and Output Signal
............................................................................
Event Manager A Functional Block Diagram
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Block Diagram of the F281x and C281x ADC Module
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ADC Pin Connections With Internal Reference
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ADC Pin Connections With External Reference
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eCAN Block Diagram and Interface Circuit
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eCAN Memory Map
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McBSP Module With FIFO
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Serial Communications Interface (SCI) Module Block Diagram
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Serial Peripheral Interface Module Block Diagram (Slave Mode)
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GPIO/Peripheral Pin Multiplexing
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TMS320x281x Device Nomenclature
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F2812/F2811/F2810 Typical Current Consumption Over Frequency
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F2812/F2811/F2810 Typical Power Consumption Over Frequency
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C2812/C2811/C2810 Typical Current Consumption Over Frequency
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C2812/C2811/C2810 Typical Power Consumption Over Frequency
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Emulator Connection Without Signal Buffering for the DSP
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F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence – Option 2
.......................................
Output Levels
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Input Levels
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3.3-V Test Load Circuit
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Clock Timing
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Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note D)
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Power-on Reset in Microprocessor Mode (XMP/MC = 1)
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Warm Reset in Microcomputer Mode
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Effect of Writing Into PLLCR Register
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IDLE Entry and Exit Timing
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STANDBY Entry and Exit Timing
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HALT Wakeup Using XNMI
...................................................................................................
PWM Output Timing
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TDIRx Timing
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EVASOC Timing
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TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View)
List of Figures
5
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