SPRS174S – APRIL 2001 – REVISED MARCH 2011
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shows the block diagram of the McBSP module with FIFO, interfaced to the F281x and C281x
version of Peripheral Frame 2.
Peripheral Write Bus
MXINT
To CPU
TX Interrupt Logic
TX FIFO
Interrupt
TX FIFO _15
TX FIFO _15
TX FIFO _1
McBSP Transmit
Interrupt Select Logic
TX FIFO _0
TX FIFO _1
TX FIFO _0
TX FIFO Registers
16
16
DXR1 Transmit Buffer
16
Compand Logic
XSR2
XSR1
FSX
CLKX
DX
DR
CLKR
FSR
RBR2 Register
16
RBR1 Register
16
DRR1 Receive Buffer
16
RX FIFO _15
LSPCLK
DXR2 Transmit Buffer
McBSP Registers
and
Control Logic
16
RSR2
16
RSR1
16
Expand Logic
McBSP
DRR2 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
RX FIFO
Interrupt
RX FIFO _15
MRINT
To CPU
RX Interrupt Logic
RX FIFO _1
RX FIFO _0
RX FIFO _1
RX FIFO _0
RX FIFO Registers
Peripheral Read Bus
Figure 4-9. McBSP Module With FIFO
74
Peripherals
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