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SPRS174S – APRIL 2001 – REVISED MARCH 2011
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3.9
PLL-Based Clock Module
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3.10 External Reference Oscillator Clock Option
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3.11 Watchdog Block
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3.12 Low-Power Modes Block
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Peripherals
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4.1
32-Bit CPU-Timers 0/1/2
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4.2
Event Manager Modules (EVA, EVB)
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4.2.1
General-Purpose (GP) Timers
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4.2.2
Full-Compare Units
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4.2.3
Programmable Deadband Generator
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4.2.4
PWM Waveform Generation
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4.2.5
Double Update PWM Mode
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4.2.6
PWM Characteristics
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4.2.7
Capture Unit
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4.2.8
Quadrature-Encoder Pulse (QEP) Circuit
...................................................................
4.2.9
External ADC Start-of-Conversion
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4.3
Enhanced Analog-to-Digital Converter (ADC) Module
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4.4
Enhanced Controller Area Network (eCAN) Module
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4.5
Multichannel Buffered Serial Port (McBSP) Module
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4.6
Serial Communications Interface (SCI) Module
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4.7
Serial Peripheral Interface (SPI) Module
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4.8
GPIO MUX
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Development Support
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5.1
Device and Development Support Tool Nomenclature
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5.2
Documentation Support
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5.3
Community Resources
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Electrical Specifications
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6.1
Absolute Maximum Ratings
..............................................................................................
6.2
Recommended Operating Conditions
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6.3
Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)
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6.4
Current Consumption
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6.5
Current Consumption Graphs
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6.6
Reducing Current Consumption
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6.7
Emulator Connection Without Signal Buffering for the DSP
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6.8
Power Sequencing Requirements
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6.9
Signal Transition Levels
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6.10 Timing Parameter Symbology
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6.11 General Notes on Timing Parameters
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6.12 Test Load Circuit
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6.13 Device Clock Table
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6.14 Clock Requirements and Characteristics
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6.14.1 Input Clock Requirements
...................................................................................
6.14.2 Output Clock Characteristics
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6.15 Reset Timing
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6.16 Low-Power Mode Wakeup Timing
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3.8.1
Loss of Input Clock
Contents
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