TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
•
EMIFA: These EMIFA signals are multiplexed with boot and configuration pins: EM_A[4], EM_A[2:0],
EM_BA[0], EM_BA[1]; therefore, they are forced 3-stated throughout RESETOUT.
–
–
–
–
–
–
Z+/Low Group: EM_A[4], EM_A[2:0]
Z+/High Group: EM_BA[0], EM_BA[1], EM_OE, EM_WE
Z+/Invalid Group: EM_D[7:0]
Z/Low Group: EM_A[21:5], EM_A[3], EM_R/W
Z/High Group:EM_CS2
Z Group: EM_WAIT/(RDY/BSY)
•
DDR2 Memory Controller:
–
–
–
–
Clock Group: DDR_CLK0, DDR_CLK0
DDR2 Z Group: DDR_DQM[3:0], DDR_DQS[3:0], DDR_D[31:0]
DDR2 Low Group: DDR_CKE, DDR_BS[2:0], DDR_A[12:0]
DDR2 High Group:DDR_CS, DDR_WE, DDR_RAS, DDR_CAS
•
•
•
PCI: All PCI pins behave according to Z Group.
I2C: All I2C pins behave according to Z Group.
JTAG: TDO, EMU0, and EMU1 pins behave according to Z Group. TCK, TDI, TMS, and TRST are
input-only pins.
•
Clock: CLKOUT0
For more information on the pin behaviors during device-level global reset, see Figure 6-7 and Figure 6-8
in Section 6.5.9, Reset Electrical Data/Timing.
6.5.9 Reset Electrical Data/Timing
Note: If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD)
resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor.
Table 6-11. Timing Requirements for Reset (see Figure 6-7 and Figure 6-8)
-400
-500
-600
NO.
UNIT
MIN
MAX
1
4
tw(RESET)
Pulse duration, POR low or RESET low
12C(1)
12C(1)
ns
ns
Setup time, boot and configuration pins valid before POR high or RESET
high(2)
tsu(CONFIG)
Hold time, boot and configuration pins valid after POR high or RESET
high(2)
5
th(CONFIG)
0
ns
(1) C = 1/MXI clock frequency in ns. The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET)
requirement.
(2) For the list of boot and configuration pins, see Table 2-5, Boot Terminal Functions.
Table 6-12. Switching Characteristics Over Recommended Operating Conditions During Reset(1)
(see Figure 6-8)
-400
-500
-600
NO.
PARAMETER
UNIT
MIN
MAX
1900C
10C
20
2
3
6
7
td(RSTH-RSTOUTH)
tw(PAUSE)
Delay time, POR high or RESET high to RESETOUT high
Pulse duration, SYSCLKs paused (low) before RESETOUT high
Delay time, POR low or RESET low to pins invalid
ns
ns
ns
ns
10C
td(RSTL-IV)
td(RSTH-V)
Delay time, POR high or RESET high to pins valid
20
(1) C = 1/CLKIN1 clock frequency in ns.
192 Peripheral Information and Electrical Specifications
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