TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.5.4 CPU Local Reset
The C64x+ DSP CPU has an internal reset input that allows a host (PCI/HPI) to control it. This reset is
configured through a register bit (MDCTL[39].LRST) in the Power Sleep Controller (PSC) module. When in
C64x+ local reset, the slave DMA port on C64x+ will remain active and the internal memory will be
accessible. For procedures on asserting and de-asserting CPU local reset by the host, see the
TMS320DM643x DMP DSP Subsystem Reference Guide (literature number SPRU978).
For information on peripheral selection at the rising edge of POR or RESET, see Section 3, Device
Configurations of this data manual.
6.5.5 Peripheral Local Reset
The user can configure the local reset and clock state of a peripheral through programming the PSC.
Table 6-4, DM6437 LPSC Assignments identifies the LPSC numbers and the peripherals capable of being
locally reset by the PSC. For more detailed information on the programming of these peripherals by the
PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (literature number SPRU978).
6.5.6 Reset Priority
If any of the above reset sources occur simultaneously, the PLLC only processes the highest priority reset
request. The rest request priorities are as follows (high to low):
•
•
•
•
Power-on Reset
Maximum Reset
Warm Reset
CPU Reset
6.5.7 Reset Controller Register
The Reset Type Status (RSTYPE) register (01C4 00E4) is the only register for the reset controller. This
register falls in the same memory range as the PLL1 controller registers (see Table 6-18 for the PLL1
Controller Registers (Including Reset Controller)). For more details on the RSTYPE register, see the .
6.5.8 Pin Behaviors at Reset
During normal operations, pins are controlled by the respective peripheral selected in the PINMUX0 or
PINMUX1 register. During device level global reset, the pin behaves as follows:
Multiplexed Boot and Configuration Pins
These pins are forced 3-stated when RESETOUT is asserted (low). This is to ensure the proper boot and
configuration values can be latched on these multiplexed pins. This is particularly useful in the case where
the boot and configuration values are driven by an external control device. After RESETOUT is
deasserted (high), these pins are controlled by their respective default peripheral.
•
Boot and Configuration Pins Group: YOUT6/GP[28], YOUT5/GP[27], YOUT4/GP[26]/(FASTBOOT),
YOUT3/GP[25]/(BOOTMODE3), YOUT2/GP[24]/(BOOTMODE2), YOUT1/GP[23]/(BOOTMODE1),
YOUT0/GP[22]/(BOOTMODE0), R0/EM_A[4]/GP[10]/(AEAW2/PLLMS2),
G1/EM_A[1]/(ALE)/GP[9]/(AEAW1/PLLMS1), B1/EM_A[2]/(CLE)/GP[8]/(AEAW0/PLLMS0),
R1/EM_A[0]/GP[7]/(AEM2), R2/EM_BA[0]/GP[6]/(AEM1), and B2/EM_BA[1]/GP[5]/(AEM0).
For information on whether external pullup/pulldown resistors should be used on the boot and
configuration pins, see Section 3.9.1, Pullup/Pulldown Resistors.
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Peripheral Information and Electrical Specifications
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