TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
At this point:
–
The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
–
The clock and reset of each peripheral is determined by the default settings of the Power and Sleep
Controller (PSC).
–
–
The PLL Controllers are operating in PLL Bypass Mode.
The C64x+ begins executing from DSPBOOTADDR (determined by bootmode selection).
After the reset sequence, the boot sequence begins. For more details on the boot sequence, see the
Using the TMS320DM643x Bootloader Application Report (literature number SPRAAG0)).
After the boot sequence, follow the software initialization sequence described in Section 3.8, Device
Initialization Sequence After Reset.
6.5.3 Maximum Reset
A Maximum (Max) Reset is initiated by the emulator or the watchdog timer (Timer 2). The effects are the
same as a warm reset, except the device boot and configuration pins are not re-latched. The emulator
initiates a maximum reset via the ICEPICK module. This ICEPICK initiated reset is non-maskable. When
the watchdog timer counter reaches zero, this will also initiate a maximum reset to recover from a runaway
condition. The watchdog timeout reset condition is masked if the TIMERCTL.WDRST bit is cleared to "0".
To invoke the maximum reset via the ICEPICK module, the user can perform the following from the Code
Composer Studio™ IDE menu: Debug→Advanced Resets→System Reset
This is the Max Reset sequence:
1. Max Reset is initiated by the emulator or the watchdog timer.
During this time, the following happens:
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–
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The reset signals flow to the entire chip resetting all the modules on chip except the emulation
logic.
The PLL Controllers are reset thereby, switching back to PLL Bypass Mode and resetting all their
registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock.
The RESETOUT pin becomes asserted (low), indicating the device is in reset.
2. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles. At the
end of these 10 cycles, the RESETOUT pin is deasserted (driven high).
At this point:
–
The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
–
The clock and reset of each peripheral is determined by the default settings of the Power and Sleep
Controller (PSC).
–
–
The PLL Controllers are operating in PLL Bypass Mode.
The C64x+ begins executing from DSPBOOTADDR (determined by bootmode selection).
After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not latched
with a Max Reset, the previous values (as shown in the BOOTCFG register) are used to select the boot
mode. For more details on the boot sequence, see the Using the TMS320DM643x Bootloader Application
Report (literature number SPRAAG0).
After the boot sequence, follow the software initialization sequence described in Section 3.8, Device
Initialization Sequence After Reset.
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Peripheral Information and Electrical Specifications
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