PGA400-Q1
SLDS186 –MARCH 2012
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Figure 6-8. Digital Interface
NOTE
If Digital Interface is used to access the internal memory, the 8051W must enter reset state
(to prevent the 8051W from accessing the memory. The 8051W operates in reset state using
the "MICRO_RESET" bit in the Micro/Interface Control Register (MICRO_IF_SEL_T).
NOTE
The internal memory space internal is accessible via the Digital Interface without the need for
the user to implement any communication software in the 8051W. The user must implement
communication software, in the form of an interupt service routine, only if the user wishes to
communicate with the PGA400-Q1 while 8051W is not in reset state. This interupt service
routine is used in conjuction with a communication buffer interface, that is available in both
the ESFR and Test Memory address spaces.
NOTE
While the 8051W is not in a reset state, it transfers data to the internal memory space using
the Digital Interface. This transfer is accomplished using the communication buffer that exists
between the Test Register memory space and the ESFR memory space (shown as COMM
BUFFER in Figure 6-8).
6.17 One-Wire Interface (OWI)
The device includes a One-Wire Interface (OWI) digital communication interface. The main function of the
OWI is to enable writes to and reads from all addresses available for OWI access. These include access
to most Test Register and ESFR memory locations.
6.17.1 Overview of OWI Interface
The OWI digital communication is a master-slave communication link in which the PGA400-Q1 operates
as a slave device only. The master device controls when data transmission begins and ends. The slave
device does not transmit data back to the master until it is commanded to do so by the master. A logic 1
(high) value on the one wire interface is defined as a recessive value, while a logic 0 (low) value on the
one-wire interface is defined as a dominant value.
26
FUNCTIONAL DESCRIPTIONS
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