5.18 P_SERR Event Disable Register
The P_SERR event disable register is used to enable/disable SERR event on the primary interface. All events are
enabled by default. See Table 5–16 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
P_SERR event disable
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
Register:
Type:
P_SERR event disable
Read-only, Read/Write
Offset:
Default:
64h
00h
Table 5–16. P_SERR Event Disable Register
BIT
TYPE
FUNCTION
7
R
Reserved. Bit 7 returns 0 when read.
Master delayed read time-out
24
6
5
R/W
0 = P_SERR signaled on a master time-out after 2 retries on a delayed read (default).
1 = P_SERR is not signaled on a master time-out.
Master delayed write time-out.
24
R/W
R/W
0 = P_SERR signaled on a master time-out after 2 retries on a delayed write (default).
1 = P_SERR is not signaled on a master time-out.
Master abort on posted write transactions. When set, bit 4 enables P_SERR reporting on master aborts on posted write
transactions.
4
0 = Master aborts on posted writes enabled (default)
1 = Master aborts on posted writes disabled
Target abort on posted writes. When set, bit 3 enables P_SERR reporting on target aborts on posted write transactions.
0 = Target aborts on posted writes enabled (default).
3
2
R/W
R/W
1 = Target aborts on posted writes disabled.
Master posted write time-out
24
0 = P_SERR signaled on a master time-out after 2 retries on a posted write (default).
1 = P_SERR is not signaled on a master time-out.
Posted write parity error
1
0
R/W
R
0 = P_SERR signaled on a posted write parity error (default).
1 = P_SERR is not signaled on a posted write parity error.
Reserved. Bit 0 returns 0 when read.
5–16
TI [ TEXAS INSTRUMENTS ]
