5.20 P_SERR Status Register
The P_SERR status register indicates what caused a SERR event on the primary interface. See Table 5–18 for a
complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
P_SERR status
R/C/U R/C/U
R
0
R/C/U
0
R/C/U
0
R/C/U
0
R/C/U
0
R
0
0
0
Register:
Type:
P_SERR status
Read-only, Read/Clear/Update
Offset:
Default:
6Ah
00h
Table 5–18. P_SERR Status Register
BIT
TYPE
FUNCTION
7
R
Reserved. Bit 7 returns 0 when read.
24
Master delayed read time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 2 retries on
a delayed read.
6
5
R/C/U
24
Master delayed write time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 2 retries on
R/C/U
R/C/U
a delayed write.
Master abort on posted write transactions. A 1 indicates that P_SERR was signaled because of a master abort on a posted
write.
4
3
2
R/C/U Target abort on posted writes. A 1 indicates that P_SERR was signaled because of a target abort on a posted write.
24
Master posted write time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 2 retries on
R/C/U
a posted write.
1
0
R/C/U Posted write parity error. A 1 indicates that P_SERR was signaled because of parity error on a posted write.
Reserved. Bit 0 returns 0 when read.
R
5.21 PM Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The capability ID
register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities
pointer and the value.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Capability ID
Read-only
DCh
01h
5–18
TI [ TEXAS INSTRUMENTS ]
